LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux IS
	PORT
	(
		a,b,c,d	: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel, cs	: IN 	STD_LOGIC;
		e,f		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
END mux;

ARCHITECTURE arch_mux OF mux IS
	
BEGIN
	process(a,sel)
	begin
		if cs = '1' then
			case sel is
				when '0' =>
					e <= a;
					f <= b;
				when '1' =>
					e <= c;
					f <= d;
				when others =>
					--
			end case;
		else
			e <= "00000000";
			f <= "00000000";
		end if;

	end process;
END arch_mux;